Oxide breakdown is one of the most threatening failure mechanisms in integrated circuits. As the oxide thickness is decreased in the sub-5 nm range, the breakdown definition itself is no longer clear and its detection becomes problematic. The present invention is related to methods of detecting the breakdown in dielectric layers, in particular oxide layers of such low thickness.
The following documents belonging to the state of the art are referred to in this section:
[1] M. Depas, T. Nigam et al., xe2x80x9cSoft breakdown of ultra-thin gate oxide layers,xe2x80x9d IEEE Trans. Elec. Dev., vol. 43, no. 9, pp. 1499-1504, 1996.
[2] E. Y. Wu et al., xe2x80x9cStructural Dependence of Dielectric Breakdown in Ultra-Thin Gate Oxides and Its Relationship to Soft Breakdown Modes and Device Failure,xe2x80x9d IEDM Tech. Dig., pp. 187-190, 1998.
[3] F. Crupi, R. Degraeve et al., xe2x80x9cOn the properties of the gate and substrate current after softbreakdown in ultrathin oxide layers,xe2x80x9d IEEE Trans. Elec. Dev., vol. 45, no. 11, pp. 2329-34, 1998.
[4]B. Weir et al., xe2x80x9cUltra-Thin Gate Dielectrics: They Break Down, but do they Fail?xe2x80x9d IEDM Tech. Dig., pp. 73-76, 1997.
[5] G. B. Alers et al., xe2x80x9cTrap Assisted Tunneling as a Mechanism of Degradaton and Noise in 2-5 nm Oxides,xe2x80x9d IRPS Proc., pp.76-79, 1998. G. B. Alers, B. E. Weir, M. A. Alam, G. L. Timp, and T. Sorch, Lucent Technologies, Murray Hill, N.J.
[6] S. Baase, Computer Algorithms, New York: Addison-Wesley, 1988, ch. 2, pp. 47-52.
All references in the text below which contain square brackets [] refer to one or more of these six documents.
An accurate determination of the gate oxide reliability is of great importance for the correct prediction of IC lifetime. In the past, the accuracy of this prediction was mainly limited by the accuracy of the extrapolation from high voltage time-to-breakdown (tBD) data to low voltage. Apart from the distinction between intrinsic and extrinsic breakdown, the intrinsic mode can be xe2x80x98softxe2x80x99 or xe2x80x98hardxe2x80x99 [1]. Since the identification of soft and hard breakdown modes (SBD and HBD, respectively), the definitions of oxide breakdown and oxide failure are no longer obvious. Defining soft breakdown (SBD) and hard breakdown (HBD) precisely turns out to be a difficult task. SBD is usually associated with a smaller current jump during a Constant Voltage Stress (CVS) or a smaller voltage drop during Constant Current Stress (CCS) compared to the HBD case. As confirmed by some research groups, the soft and hard breakdowns are caused by the same physical mechanism: SBD is considered to be a breakdown without the thermal runaway effects that lead to a low-resistance breakdown path connecting gate and substrate [1]. Based on this assumption and the observation that hard breakdown is dominant in small geometry transistors [2], we consider the time-to-first breakdown, regardless of whether it is soft or hard, as time-to-breakdown in this description.
This leaves the problem of correctly determining the time-to-soft breakdown. SBD occurs when the generated density of traps during a CVS or CCS has sufficiently increased to generate (at some random place on the capacitor area) a breakdown path of traps connecting anode with cathode. SBD is (just as HBD) a local event. As a consequence the Ig-Vg characteristic of the SBD is, apart from some statistical fluctuations, independent of the test area [3]. This IV-curve is the most unambiguous signature of an SBD event, and measuring it is therefore the most direct way to detect SBD. However, this approach has the disadvantage that the stress needs to be interrupted at regular time intervals to measure the low voltage current. This is time-consuming and might influence the time-to-breakdown, especially when the current or voltage overshoot at the start of each stress interval is not well-controlled.
A better method is to determine the breakdown event real-time by monitoring the most adequate parameter. In [4,5], it has been observed that SBD is accompanied by a gate current noise increase. This increase has been used as a trigger for SBD detection [5].
However, simple noise monitors like the variance of current values during constant voltage stress are too sensitive to pre-BD events and spikes, resulting in false BD triggers.
The present invention aims to provide an accurate method for detecting soft breakdown events in integrated circuit devices, wherein a reduced sensitivity is present to pre-breakdown events, resulting in a lower probability of erroneous breakdown detection.
The present invention is related to a method for detecting breakdown in a dielectric layer, comprising the steps of:
applying a signal to said dielectric layer,
measuring a plurality of sets of readings having values, which are in relation to said signal,
searching and identifying outlier readings in each of said sets, said outlier readings being defined by the fact that they have values which are significantly higher or lower than the majority of the values of said set,
selecting from each of said sets, one reading which is not one of said outlier readings,
comparing the value of said one selected reading to a reference value, so that the exceeding of said value leads to the conclusion that a predefined probability is present for having a breakdown state in said layer.
According to the preferred embodiment, the value of said one selected reading is the median (mr) of the values of said set of readings.
Preferably, for each set of readings, a second set of readings is measured, said second set consisting of at least twice the amount of readings of said first set of readings, and wherein said reference value is a function of the value of a selected reading of said second set, said selected reading being selected in the same way as said selected reading of said first set.
According to the preferred embodiment, the value of said selected reading of said second set is the median (mref) of the values of said second set of readings.
Preferably, said function is a linear function f(mref)=amref, with a predefined factor xe2x80x98axe2x80x99.
In the method of the invention, the sorting of said sets of readings is preferably done according to an indirect insertion sorting technique.
According to a first embodiment, said signal is a voltage signal, corresponding to a voltage difference across said layer, and said readings are absolute values of the change of the current flowing through said layer, as a consequence of said voltage signal, said change being calculated on the basis of a set of current readings, as the difference between two subsequent current readings of said set.
According to a second embodiment, said signal is a current signal, corresponding to a current flowing through said layer, and said readings are absolute values of the change of the voltage across said layer, as a consequence of said current signal, said change being calculated on the basis of a set of voltage readings, as the difference between two subsequent voltage readings of said set.
The invention is also related to an apparatus for detecting breakdown in a dielectric layer, said apparatus comprising
means for applying a test signal to a dielectric layer,
means for measuring a number of sets of readings,
means for searching and selecting one reading in each set,
means for comparing the value of said one selected reading to a reference value,
output means for indicating that a breakdown state is present in said layer, with a given probability, on the basis of said comparison.
According to the preferred embodiment, said means for calculating comprises means for sorting said sets of readings according to an indirect insertion sorting technique.
In an apparatus of the invention, said test signal may be a voltage signal, corresponding to a voltage difference across said layer, in which case said readings are absolute values of current changes.
Alternatively, said test signal may be a current signal, corresponding to a current through said layer, in which case said readings are absolute values of voltage changes.